1. Field of the Invention
The invention relates in general to a metal of fabricating a metal oxide semiconductor (MOS), and more particularly to a method of fabricating a self-align contact (SAC).
2. Description of the Related Art
In the conventional method of fabricating a self-align contact, a silicon oxide layer is formed as a thick cap oxide layer on a poly-silicon layer. With the formation of the thick cap layer, the damage of a gate during the process of forming a self-align contact is prevented.
FIG. 1A to FIG. 1F show the cross sectional views of forming a MOS with a self-align contact. Referring to FIG. 1A, a substrate 100 having a lightly doped P-well, or a P-type semiconductor is provided. A gate 102 is formed on the substrate 100. The gate 102 comprises a gate oxide 104 on the substrate 100, a doped poly-silicon layer 106 on the gate oxide layer 104, a metal silicide layer 107 on the doped poly-silicon layer 106, and a thick cap layer 108, such as a silicon oxide layer on the metal silicide layer 107. The gate oxide layer having a thickness of about 30 .ANG. to 200 .ANG. is formed in an oxygen environment at about 800.degree. C. to 1000.degree. C. The doped poly-silicon layer 106 having a thickness of about 1000 .ANG. to 3000 .ANG., or even as thick as 1500 .ANG. to 2500 .ANG., is formed by plasma enhanced chemical vapor deposition (LPCVD). Arsenic ions or phosphorous ions are in-situ doped during the deposition of the poly-silicon layer, or implanted into the poly-silicon layer 106 after the deposition. The metal silicide layer 107 having a thickness of 1000 .ANG. to 3000 .ANG. is tungsten silicide, titanium suicide, or molybdenum silicide. The thick cap layer 108 is a silicon oxide layer formed by chemical vapor deposition. Using the thick cap layer 108 as a mask, the source/drain region 110 is formed by doping, such as doped with N-type arsenic ions or phosphorous ions.
Referring to FIG. 1B, a first dielectric layer 112 is formed over the substrate 100, for example, a silicon oxide layer formed by chemical vapor deposition. Referring to FIG. 1C, anisotropic etching, for example, reactive ion etching, is performed to etch back the first dielectric layer 112. The source/drain region 110 is then exposed, and a spacer 112a on a side wall of the gate 102 is formed. The formation of the spacer 112a is not only a protection structure of the gate 102, but is also advantageous to the formation of heavily doped source/drain region. Using spacer 112a as a mask, a heavily doped source/drain region 114 is formed by heavily doping with, for example, a high concentration of N-type arsenic ions.
Referring to FIG. 1D, a second dielectric layer 116 is formed over the substrate 100, for example, a silicon oxide layer by chemical vapor deposition using a mixture of silane and oxygen as a reactive gas. A photo-resist layer is formed and patterned as the photo-resist layer 117 for the formation of a self-align contact.
Referring to FIG. 1E, the second dielectric layer 116 is etched until exposing the source/drain region 114 to form a self-align contact window 118 which penetrates through the second dielectric layer 116. The etch step is, for example, an anisotropic plasma etch step. The photo-resist layer 117 is then removed.
Referring to FIG. 1F, a doped poly-silicon layer 119 is formed over the substrate 100. Using conventional photolithography to patterned the doped poly-silicon layer 119, a self-align contact 122 is formed.
In the above conventional method, after the spacer is formed by patterning the first poly-silicon layer, the second dielectric layer is formed as a mask for the formation of the contact window. The second dielectric layer is then removed after the formation of the contact. The process is tedious, and the fabrication cost is high due to the waste of material. In case that the second poly-silicon layer is not removed completely during the process of forming a self-align contact, an additional spacer is formed. Consequently, the surface area of the self-align contact window is reduced, and the contact resistance is increased. In addition , since the MOS is formed before the formation of the self-align contact, the doped region is expanded in the subsequent thermal process due to the diffusion of dopant. Therefore, the quality of the devices is degraded.